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PG32400K, 400MHz: 32 channel USB port logic analyzer with graphics generator
Sampling rate: 400MHz/s, bandwidth: 200MHz, storage depth: 1024K, 32 channels, with pattern generator
Product details
PG series virtual logic analyzer, similar to a graphic generator.
PG-32400K 400MHz sampling, 512K storage The price is: 2900 yuan
PG-32400K 400MHz sampling, 2048K storage The price is 3900 yuan
Technical specifications: (Chinese and English interface)
High speed sampling rate up to: PG32400 series: 400MSa/s
32 通道
Storage depth per channel: PG32400 K series: 512K
PG32400 M series: 2048K
Continuously variable front/rear trigger position
High impedance probe reduces interference between the tested circuits (100Kohm)
Variable threshold voltage
status display
Time series display
Mixed mode display
Multiple triggering methods
High data bandwidth up to 200 MHz
External high-speed clock input
Establish I2C analysis
Can use one probe to capture both timing and status simultaneously
The logic analyzer is equipped with high-quality test clips and wiring at the same time
With pattern generator
USB power does not require an external power source.
Hardware technical specifications:
| Model: | PG-32400 K [512K] | PG-32400M [2 Mega] | Remarks: | |
| Update rate of pattern generator: Clock sampling rate in logic analyzer: | From 1Sa/s to 400 MSa/s | Same steps 1, 2, and 5 | ||
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| Sampling rate of logic analyzer external clock: | Up to 200 MSa/s | External clock Ext. clk0 and external clock Ext.clk1 are combined with standard TTL (1.4V threshold voltage) OR, NOR, AND, NAND | ||
| Record length: | 32通道: 256K x 2 / 通道 16通道: 512K x 2 / 通道 | 32通道: 1M x 2 / 通道 16通道: 2M x 2 / 通道 | Total storage capacity=(256K/1M) x 2 x 32 channels | |
| Definition of each logical channel: | Ch 0~Ch31 (graphic generation+logical channel) GOE ˜ (All outputs allow low level to be valid) Two external clocks | 32 bidirectional logical channels default to external clock Ext.clk0, Ext.clk1 (OR, NOR, AND, NAND) | ||
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| I/O bandwidth | DC to 200 MHz | Same<30pF load | ||
| Input impedance: | 100 KΩ // 8pF | Same as the 100 Ohm series | ||
| maximum. Input voltage | +5.5V to -0.5 V | | ||
| I/O type (drive current, threshold voltage) | LVC1.5V (10mA, 0.75V) LVC1.8V (12mA, 0.9V) LVC2.5V (16mA, 1.2V) LVC3.3V (20mA, 1.4V) SSTL2 II 2.5V (16mA, 0 to 2.4V) SSTL3 II 3.3V (16mA, 0 to 3V) | Drive current (Balanced source and receiver) Standard logic input/output I/O | ||
| output delay | Typical value<10 ns | Input/output bidirectional change | ||
| Channel slope | Typical value<200 ps | | ||
| | | | ||
| Trigger position: | -67M to 256K/512K | -67M 到 1 Mega / 2Mega | Users can define any trigger location | |
| maximum. Trigger rate: | 100MHz / 10ns | | ||
| Trigger limit: | 0, 1, x (arbitrary) Set all trigger channels | Simultaneously triggering the graphic generator and logic channel | ||
| Power support: | No need for external power supply | From USB port<450mA | ||
| Trigger edge: | Triggered when it becomes' true 'or' false ' | |||
| Trigger method: | Single time method: Capture the value of the data buffer once when the triggering condition is met. Normal method: When the triggering condition is met, capture the value of the data buffer once, and then repeat the capture. Automatic mode: If capture is continuously performed within a set time | |||
| Timing status: | The data of 32 channels can be displayed using time-series waveforms, and the color of each channel can be independently adjusted. Each channel name can be displayed with up to 9 letters and can be displayed in any sequence. Users can also integrate and observe in ASCII binary, octal, hexadecimal, and user-defined mnemonic formats. Display the timing between cursor A and the trigger cursor. The scaling ratio is 1/50 to 50 times in the horizontal direction and 1 to 2 times in the vertical direction. The color of each channel can be independently set | |||
| Status List: | Channel data can be displayed in groups and can also be displayed in ASCII, binary, octal, hexadecimal, user-defined mnemonic formats. The data for each channel can also be displayed in a user-defined sequence, displaying the timing between cursor A, cursor B, and touch cursor | |||
| Net weight: | 0．5KG | |||
| Size: | 107mm x 77mm x 16mm | |||
| Print output: | Windows software status and timing waveforms can be printed on any printer compatible with Windows. | |||
| Output data: | Data and settings can be suffixed Save in LA format for future display and analysis, and data can also be saved in Excel format for other programs to call. | |||
| Software: | Support: WINDOWS2000/XP | |||
| International Quality | Domestic prices | |||
Series model:
| Series models (USB port) basic cache | sampling rate | 通道 | Maximum storage | Actual measured bandwidth | Trigger the door Voltage limit | trigger function | Full set price including accessories |
| PG32200K/256K | 200MHz | 32 | 256K(max) | 100MHz | 0 ~ +3V | complex | 2900 yuan |
| PG32200M/1M | 200MHz | 32 | 1M(max) | 100MHz | 0 ~ +3V | complex | 3900 yuan |
| PG32400K/512K | 400MHz | 32 | 512K(max) | 200MHz | 0 ~ +3V | complex | 4900 yuan |
| PG32400M/2M | 400MHz | 32 | 2M(max) | 200MHz | 0 ~ +3V | complex | 5900 yuan |
| LA2132K/256K (There are three models available) LA2132K2/256K LA2132K8/256K LA2132K512/256K | 250MHz | 32 | 256K(max) | 125MHz Under LVDS 200MHz | -3.7 ~ +1.9V | K2, K8, and K512 are level 2, level 8, and level 512 triggers, respectively | 900 yuan K2 model 1900 yuan K8 model 2900 yuan K512 model |
| LA2132M/1M series (There are three models available) LA2132M2/1M LA2132 M8/1 M LA2132 M512/1M | 500MHz | 32 | 1M(max) | 125MHz Under LVDS 200MHz | -3.7 ~ +1.9V | M2, M8, M512 are level 2, level 8, and level 512 triggers, respectively | 1900 yuan M2 model 2900 yuan M8 model 3900 yuan M512 model |
| LA2132G/4M series (There are three models available) LA2132G2/1G LA2132 G8/1 G LA2132 G512/1G | 1GHz | 32 | 4M(max) | 125MHz Under LVDS 200MHz | -3.7 ~ +1.9V | G 2, G 8, and G 512 are level 2, level 8, and level 512 triggers, respectively | 2900 yuan G2 model 3900 yuan G8 model 4900 yuan G512 model |
Large capacity storage helps users capture all the data they need
PG32200/32400 has a large storage space, allowing users to trigger a large number of events around the trigger point,
Sometimes it can be difficult for users to pinpoint the exact event that triggered the location, but with our system, users have no access to it
Need to know the exact location of the trigger, as the PG32200/32400 logic analyzer has a long storage buffer
The area saves the trigger content, but of course, when users capture long trigger events, it may cause other analyses to be unable to proceed,
Or in the case of exceeding storage space, users can obtain more detailed content by increasing the sampling rate.
Leveraging the powerful features of a PC
PC based instruments provide very familiar interfaces, as the instrument uses a PC, it is connected through cables or communication
It is normal for software to transmit data to a PC for analysis, and the advantage of PC based instruments is also that it
No major cost is required, hardware does not need to be upgraded, only software upgrade is needed, and software upgrade is free
BBS or web download. The PG32200/32400 logic analyzer fully utilizes the large color display to show more
Data, not only can all 24 channels be displayed simultaneously in different colors on the monitor, but there is also enough space for display
Display system parameters, users only need to input data with the keyboard, without the need for knobs or multiple menus, any parameter changes can be made
It is very fast, as they continuously update the screen display waveform based on changes in the sampling buffer data, so,
The PG32200/32400 logic analyzer is easy to use, intuitive, and easy to learn.
High clock speed widens the measurement range for users
In theory, the sampling rate of a logic analyzer should be twice the measured frequency, but in reality, if we want to achieve precise
The measurement should be four times the measured signal. PG32200/32400 has a sampling rate of 200/400MHz/s, so it can be logarithmic
According to subtle capture.
| Low sampling rate (good signal quality) | High sampling rate (with spikes) |
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High sampling rate (with spikes)
Users can better capture burrs by using fast sampling.
It is very easy to observe and control data using the Windows interface
Timing Window
The collected data is displayed as a time-series waveform, and each channel can be defined as its favorite color and channel name,
You can also observe the values of each cursor and scrollbar, and the display window can be zoomed in or out, or display several values in the window
Sample the waveform or the waveform of the entire data buffer.
Channel groups are displayed in hexadecimal format
 |  |
Channel group displayed in wave form
Status Window
The collected data is displayed in numerical format in groups, including ASCII code, binary, octal, hexadecimal,
Decimal or user-defined characters The collected data forms a user-defined array.
Control and setting of cursor
The current position of the cursor is displayed in the right window. Select a specific cursor or display window and click the arrow to change it precisely
The current position of the cursor can also be quickly repositioned by clicking and dragging the cursor with the mouse. This position is correct
At the trigger point, it can be displayed both absolutely and relatively using time units or data sampling numbers.
search
It is very easy to classify data collected through the search function, and users can determine a search pattern, including any
The fuzzy bits of the base address number displayed can be searched by clicking the "forward" or "backward" button.
File saving and output
Data storage is convenient for future viewing or sharing with other engineers. Users can also save data in CSV format for their convenience
It is used in programs such as MathCAD, Excel, Word, etc. The image displayed on the screen can also be pasted onto
In programs such as Word, Excel, etc.
Logic analyzer: test clip
The PG32200/32400 logic analyzer is equipped with a complete set of color test clamps and connecting wires. The test clamp head is composed of two steel needles
The structure is very hard and can change into various sizes and shapes. This precision testing clip can test the connection density
For high IC or testing with very difficult surface connection, the test line can be connected to both ends of the test clip, as shown in the figure: right
Logic analyzer: connection line
The connecting wire is the connection between the logic analyzer and each test clip, or directly connected to the test circuit. each
Each data channel provides one wire, with two ground wires, each approximately 10 inches long, and one connection at each end of the wire
Plug, one end of the wire is inserted into the connection of the logic analyzer, and the other end is connected to the test clip or directly inserted into the tested circuit.
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